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? semiconductor ML63512A/63514a 1/29 general description the ML63512A/63514a is a cmos 4-bit microcontroller with built-in level detector and operates at 0.9 v (min.). the ML63512A/63514a is an m6351x series mask rom-version product of olms-63k family, which employs oki's original cpu core nx-4/250. the program memory capacity and data memory capacity of the ML63512A differ from those of the ml63514a. 48-pin tqfp and 64-pin tqfp packages are available for the ML63512A and ml63514a. features ? extensive instruction set 407 instructions transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, rom table reference, stack operations, flag operations, jump, conditional branch, call/return, control. ? wide variety selection of addressing modes indirect addressing of four data memory types, with current bank register, extra bank register, hl register and xy register. data memory bank internal direct addressing mode. ? processing speed two clocks per machine cycle, with most instructions executed in one machine cycle. minimum instruction execution time : 61 m s (@ 32.768 khz system clock) 1 m s (@ 2 mhz system clock) ? clock generation circuit low-speed clock : crystal oscillation or rc oscillation selectable by mask option (30 to 80 khz) high-speed clock : ceramic oscillation or rc oscillation selectable by mask option (2 mhz max.) ? program memory space ML63512A: 4k words ml63514a: 8k words basic instruction length is 16 bits/1 word ? data memory space ML63512A: 128 nibbles ml63514a: 256 nibbles ? semiconductor ML63512A/63514a 4-bit microcontroller with built-in level detector, melody circuit, and comparator, operating at 0.9 v (min.) e2e0057-29-71 this version: jul. 1999 previous version: jun. 1999
? semiconductor ML63512A/63514a 2/29 ? stack level call stack level : 16 levels register stack level : 16 levels ? i/o ports input ports: selectable as input with pull-up resistor/high-impedance input output ports: n-channel open drain output (can directly drive leds) input-output ports: selectable as input with pull-up resistor/high-impedance input selectable as n-channel open drain output/cmos output can be interfaced with external peripherals that use a different power supply than this device uses. (power to the output port is supplied from v ddi (separate power suply)) number of ports: (for 48-pin packages) input port : 1 port 4 bits output port : 1 port 4 bits input-output port : 6 ports 4 bits (for 64-pin packages) input port : 1 port 4 bits output port : 1 port 4 bits input-output port : 9 ports 4 bits ? melody output function melody sound frequency : 529 to 2979 hz (@ 32.768 khz) tone length : 63 varieties tempo : 15 varieties melody data : stored in the program memory number of ports : 1 (dedicated pin) buzzer driver signal output : 4 khz (@ 32.768 khz) ? level detector conversion time : approx. 183 m s (@ 32.768 khz) dedicated input pins : 2 pins (switched by software; for the secondary functions of the input ports) detection level : 12 levels ? comparator offset voltage : 50 mv max. (v dd = 1.5 v) comparison time : approx. 183 m s (@ 32.768 khz) number of channels : 1 (for the secondary functions of the input ports) ? reset function reset through resetb pin (resetb pin can be pulled up by mask option) ? power supply backup backup circuit (voltage multiplier) enables operation at 0.9 v minimum
? semiconductor ML63512A/63514a 3/29 ? timers and counter 8-bit timer 2 selectable as auto-reload mode/capture mode/clock frequency measurement mode 15-bit time base counter 1 1 hz, 2 hz, 4 hz, 8 hz, 16 hz, 32 hz, 64 hz, 128 hz, 256 hz, 512 hz, 1 khz, and 2 khz signals can be read (@ 32.768 khz) ? serial port mode : selectable as uart mode/synchronous mode uart communication speed : 2tbcclk, tbcclk, 1/2tbcclk, timers 0 & 1 overflow 24 kbps max. (when 2tbcclk @ 80 khz selected) clock frequency in synchronous mode : 30 to 80 khz (internal clock mode), external clock frequency data length : 5 to 8 bits ? interrupt sources external interrupt (4 sources) : selectable as rising edge/falling edge/both rising and falling edges internal interrupt (10 sources) : time base interrupt 4 (2, 4, 16, and 32 hz @ 32.768 khz) timer interrupt 2 level detector interrupt 1 serial port reception interrupt 1 serial port transmission interrupt 1 melody end interrupt 1 ? operating temperature C20 to +70 c ? supply voltage when backup used : 0.9 to 1.8 v (maximum operating frequency 1 mhz) when backup not used : 1.8 to 3.5 v (when level detector or comparator is used, maximum operating frequency 2 mhz) 1.8 to 5.5 v (when level detector and comparator are not used, maximum operating frequency 2 mhz) ? package options: 48-pin plastic tqfp (tqfp48-p-0707-0.50-k) : (product name: ML63512A-xxxtb, ml63514a-xxxtb) 64-pin plastic tqfp (tqfp64-p-1010-0.50-k) : (product name: ML63512A-xxxtp, ml63514a-xxxtp) xxx indicates a code number.
? semiconductor ML63512A/63514a 4/29 block diagram an asterisk (*) indicates the port secondary function. the power to the circuits corresponding to the signal names inside is supplied from v ddi (power supply for interface). rom ML63512A: 4kw ml63514a: 8kw bus con- trol mie xt0 xt1 osc0 osc1 tbcclk * hsclk * osc cbr ebr l c g z alu ra a ir instruction decoder ram ML63512A: 128n ml63514a: 256n nx-4/250 resetb rst v ddi pc h y x timing con- trol sp rsp stack cal: 16-level reg: 16-level timer 8bit 2 rxc * txc * rxd * txd * 2 int sio tm0cap/tm1cap * tm0ovf/tm1ovf * t0ck * t1ck * 2 int i/o port p0.0-p0.3 p1.0-p1.3 p2.0-p2.3 p3.0-p3.3 p4.0-p4.3 p5.0-p5.3 p6.0-p6.3 = p9.0-p9.3 = pa.0-pa.3 = 4 int data bus tbc 4 int int 1 v ss melody md 1 int tst1b tst tst2b p7.0-p7.3 int input port p8.0-p8.3 output port ldin0 * level detector ldin1 * cmpin * cmp cmpref * v ddh v dd cb1 cb2 back- up v ddl vr = port 6 (p6.0 to p6.3), port 9 (p9.0 to p9.3) and port a (pa.0 to pa.3) are only provided for the 64- pin packages.
? semiconductor ML63512A/63514a 5/29 pin configuration (top view) 48-pin plastic tqfp p3.0/rxd 1 p3.1/txc 2 p3.2/rxc 3 p3.3/txd 4 p4.0 5 p4.1 6 p4.2 7 p4.3 8 p5.0 9 p5.1 10 p5.2 11 p5.3 12 md resetb osc1 osc0 v ss tst2b tst1b xt1 xt0 v ddl cb2 cb1 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p1.0/tm0cap/tm0ovf p1.1/tm1cap/tm1ovf p1.2/t0ck p1.3/t1ck p2.0/tbcclk p2.1/hsclk p2.2 p2.3 v ddh v dd v ss v ddi p8.3 p8.2 p8.1 p8.0 p7.3/ldin1 p7.2/ldin0 p7.1/cmpref p7.0/cmpin
? semiconductor ML63512A/63514a 6/29 pin configuration (top view) (continued) 64-pin plastic tqfp note: pins marked as (nc) are no-connection pins which are left open. pa.2 1 pa.3 2 p3.0/rxd 3 p3.1/txc 4 p3.2/rxc 5 p3.3/txd 6 p4.0 7 p4.1 8 p4.2 9 p4.3 10 p5.0 11 p5.1 12 p5.2 13 p5.3 14 p9.1 p9.0 md resetb osc1 osc0 v ss tst2b tst1b xt1 xt0 v ddl cb2 cb1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 51 52 53 54 55 56 57 58 59 60 61 62 63 64 30 29 28 27 26 25 24 23 22 21 20 19 18 17 p0.0/int0 p0.1/int1 p0.2/int2 p0.3/int3 p1.0/tm0cap/tm0ovf p1.1/tm1cap/tm1ovf p1.2/t0ck p1.3/t1ck p2.0/tbcclk p2.1/hsclk p2.2 p2.3 pa.0 pa.1 v ddh v dd v ss v ddi p8.3 p8.2 p8.1 p8.0 p7.3/ldin1 p7.2/ldin0 p7.1/cmpref p7.0/cmpin p6.3 p6.2 p6.0 15 p6.1 16 (nc) (nc) 34 33 49 50 32 31 p9.2 p9.3 (nc) (nc)
? semiconductor ML63512A/63514a 7/29 pin descriptions the basic functions of each pin of the ML63512A/63514a are described in table 1. a symbol with a slash (/) denotes a pin that has a secondary function. refer to table 2 for secondary functions. for type, "" denotes a power supply pin, "i" an input pin, "o" an output pin, and "i/o" an input- output pin. for pin, "tb" denotes a 48-pin flat package (48tqfp), and "tp" a 64-pin flat package (64tqfp). table 1 pin descriptions (basic functions) function symbol tb type v dd 23 v ss 22, 32 power supply v ddi 21 v ddl 27 v ddh 24 cb1 25 cb2 26 xt0 28 i oscillation xt1 29 o osc0 33 i osc1 34 o test tst1b 30 i tst2b 31 i reset resetb 35 i melody md 36 o description positive power supply negative power supply positive power supply pin for external interface (port8 supply) positive power supply pin for internal logic (internally generated). a capacitor c l (0.1 m f) should be connected between this pin and v ss . voltage multiplier pin for power supply backup (internally generated). a capacitor c h (1.0 m f) should be connected between this pin and v ss . pins to connect a capacitor for voltage multiplier. a capacitor (1.0 m f) should be connected between cb1 and cb2. low-speed clock oscillation pins. crystal oscillation or rc oscillation is selected by the mask option. if crystal oscillation is selected, connect a crystal between xt0 and xt1, and connect capacitor (c g ) between xt0 and v ss . if rc oscillation is selected, connect external oscillation resistor (r crl ) between xt0 and xt1. high-speed clock oscillation pins. ceramic oscillation or rc oscillation is selected by the mask option. if ceramic oscillation is selected, connect a ceramic resonator between osc0 and osc1, and connect capacitor (c l0 , c l1 ) between osc0 and v ss , osc1 and v ss . if rc oscillation is selected, connect external oscillation resistor (r crh ) between osc0 and osc1. input pins for testing. a pull-up resistor is internally connected to these pins. reset input pin. setting this pin to "l" level puts this device into a reset state. then, setting this pin to "h" level starts executing an instruction from address 0000h. an internal or external pull-up resistor is selected by mask option. melody output pin (non-inverted output) tp 29 28, 42 27 37 30 35 36 38 39 43 44 40 41 45 46 pin
? semiconductor ML63512A/63514a 8/29 table 1 pin descriptions (basic functions) (continued) function symbol tb type p0.0/int0 37 i/o port description 4-bit input-output ports. in input mode, pull-up resistor input or high-impedance input is selectable for each bit. in output mode, n-channel open drain output or cmos output is selectable for each bit. tp 51 pin p0.1/int1 38 52 p0.2/int2 39 53 p0.3/int3 40 54 p1.0/ tm0cap/ tm0ovf 41 55 p1.1/ tm1cap/ tm1ovf 42 56 p1.2/t0ck 43 57 p1.3/t1ck 44 58 p2.0/tbcclk 45 59 p2.1/hsclk 46 60 p2.2 47 61 p2.3 48 62 p3.0/rxd 1 3 p3.1/txc 2 4 p3.2/rxc 3 5 p3.3/txd 4 6 p4.0 5 7 p4.1 6 8 p4.2 7 9 p4.3 8 10 p5.0 9 11 p5.1 10 12 p5.2 11 13 p5.3 12 14 i/o i/o i/o i/o i/o
? semiconductor ML63512A/63514a 9/29 table 1 pin descriptions (basic functions) (continued) 4-bit output port. n-channel open drain output. function symbol tb type p6.0 i port description 4-bit input-output port. in input mode, pull-up resistor input or high-impedance input is selectable for each bit. in output mode, n-channel open drain output or cmos output is selectable for each bit. note that these pins are available for only a 64-pin package. tp 15 pin p7.0/cmpin 13 19 p7.1/cmpref 14 20 p7.2/ldin0 15 21 p7.3/ldin1 16 22 p8.0 17 23 p8.1 18 24 p8.2 19 25 p8.3 20 26 4-bit input port. pull-up resistor input or high-impedance input is selectable for each bit. i/o o p6.1 16 p6.2 17 p6.3 18 p9.0 47 p9.1 48 p9.2 49 p9.3 50 pa.0 63 pa.1 64 pa.2 1 pa.3 2 4-bit input-output ports. in input mode, pull-up resistor input or high-impedance input is selectable for each bit. in output mode, n-channel open drain output or cmos output is selectable for each bit. note that these pins are available for only a 64-pin package. i/o i/o
? semiconductor ML63512A/63514a 10/29 table 2 shows the secondary functions of each pin of the ML63512A/63514a. table 2 pin descriptions (secondary functions) function symbol type description tb tp pin p0.0/int0 37 51 capture external 0 interrupt input pin. edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. i p0.1/int1 38 52 external 1 interrupt input pin. edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. p0.2/int2 39 53 external 2 interrupt input pin. edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. p0.3/int3 40 54 p1.0/tm0cap 41 55 i timer 0 (tm0) capture trigger input pin. p1.1/tm1cap 42 56 i timer 1 (tm1) capture trigger input pin. external interrupt external 3 interrupt input pin. edge detection can be selected from one of a rising edge, a falling edge, or both rising and falling edges. i i i p1.0/tm0ovf 41 55 o timer 0 (tm0) overflow flag output pin. p1.1/tm1ovf 42 56 o timer 1 (tm1) overflow flag output pin. p1.2/t0ck 43 57 i timer 0 (tm0) external clock input pin. p1.3/t1ck 44 58 i timer 1 (tm1) external clock input pin. timer p2.0/tbcclk 45 59 o low-speed oscillation clock output pin. p2.1/hsclk 46 60 o high-speed oscillation clock output pin. oscillation output p3.0/rxd 1 3 i serial port receive data input pin. sync serial port clock input-output pin. transmit sync clock input-output pin when a serial port is used synchronously. transmit clock output when this device is used as a master processor. transmit clock input when this device is used as a slave processor. p3.1/txc 2 4 i/o sync serial port clock input-output pin. receive sync clock input-output pin when a serial port is used synchronously. receive clock output when this device is used as a master processor. receive clock input when this device is used as a slave processor. p3.2/rxc 3 5 i/o p3.3/txd 4 6 o serial port transmit data output pin. serial port p7.0/cmpin 13 19 i comparator analog input pin. p7.1/cmpref 14 20 i comparator reference voltage input pin. comparator p7.2/ldin0 15 21 i level detector analog input pin. p7.3/ldin1 16 22 i level detector analog input pin. level detector
? semiconductor ML63512A/63514a 11/29 absolute maximum ratings parameter symbol condition rating unit power supply voltage 1 v dd C0.3 to +5.8 power supply voltage 2 ta = 25c v ddi v C0.3 to +5.8 power supply voltage 3 ta = 25c v ddh v C0.3 to v dd + 0.3 input voltage 1 v dd input, ta = 25c v in1 v C0.3 to v ddi + 0.3 input voltage 2 v ddi input, ta = 25c v in2 v C0.3 to v dd + 0.3 output voltage 1 v dd output, ta = 25c v out1 v C0.3 to v ddi + 0.3 output voltage 2 v ddi output, ta = 25c v out2 v C0.3 to v ddh + 0.3 output voltage 3 v ddh output, ta = 25c v out3 v C55 to +150 storage temperature t stg c (v ss = 0 v) C0.3 to +5.8 power supply voltage 4 ta = 25c v ddl v C0.3 to +5.8 ta = 25c v 60 power dissipation ta = 25c p d mw
? semiconductor ML63512A/63514a 12/29 recommended operating conditions ? when backup is used v ddi 0.9 to 3.5 v crystal oscillation frequency f xt 30 to 80 khz low-speed rc oscillator frequency f crl parameter symbol condition range unit operating temperature t op C20 to +70 c v dd 0.9 to 1.8 v operating voltage (v ss = 0 v) external high-speed rc oscillator resistance r crh 32 khz r crl = 1 m w 10% 100 to 300 k w v dd = 0.9 to 1.8 v v ddi 1.8 to 5.5 crystal oscillation frequency f xt 30 to 80 khz low-speed rc oscillator frequency f crl khz parameter symbol condition range unit operating temperature t op C20 to +70 c v dd 1.8 to 3.5 operating voltage (v ss = 0 v) external high-speed rc oscillator resistance r crh k w 32 r crl = 1 m w 10% 15 to 300 v dd = 1.8 to 5.5 v 300k to 1m v dd = 2.2 to 5.5 v 200k to 2m v dd = 2.7 to 5.5 v ceramic oscillation frequency f cm hz when level detector and comparator are not used 1.8 to 5.5 v ? when backup is not used
? semiconductor ML63512A/63514a 13/29 parameter symbol condition mea- suring circuit (v dd = v ddi = 1.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) unit max. typ. min. 5.8 9.0 15.0 5.3 5.3 5.3 4.8 supply current 1 i dd1 cpu is in halt state high-speed oscillation stop level detector stop m a supply current 2 i dd2 cpu operating high-speed oscillation stop level detector stop 35.0 10.0 supply current 3 i dd3 cpu operating at low speed high-speed oscillation stop level detector active (for a soft duty of about 3%) m a 750.0 550.0 supply current 4 i dd4 cpu operating at high speed high-speed rc oscillation r crh = 100 k w m a 1 ta = 25c ta = C20 to +50c ta = C20 to +70c 14.0 16.0 24.0 13.0 13.0 13.0 12.0 m a ta = 25c ta = C20 to +50c ta = C20 to +70c electrical characteristics dc characteristics ? when backup is used ? when backup is not used parameter symbol condition mea- suring circuit (v dd = v ddi = 3.0 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) unit max. typ. min. 2.7 7.0 10.0 2.4 2.4 2.4 2.1 supply current 1 i dd1 cpu is in halt state high-speed oscillation stop level detector stop m a supply current 2 i dd2 cpu operating high-speed oscillation stop level detector stop 25.0 6.0 supply current 3 i dd3 cpu operating at low speed high-speed oscillation stop level detector active (for a soft duty of about 3%) m a 550.0 410.0 supply current 4 i dd4 cpu operating at high speed high-speed rc oscillation r crh = 100 k w m a 1 ta = 25c ta = C20 to +50c ta = C20 to +70c 7.0 9.0 15.0 6.0 6.0 6.0 5.0 m a ta = 25c ta = C20 to +50c ta = C20 to +70c 1000.0 850.0 supply current 5 i dd5 cpu operating at high speed high-speed ceramic oscillation (ceramic oscillation, 2 mhz) m a
? semiconductor ML63512A/63514a 14/29 dc characteristics (continued) parameter (pin name) v ddh voltage v ddl voltage crystal oscillation start voltage crystal oscillation hold voltage external crystal oscillator capacitance internal crystal oscillator capacitance internal high-speed rc oscillator capacitance input pin capacitance (p0.0 to p0.3) (p1.0 to p1.3) (p7.0 to p7.3) (p9.0 to p9.3) (pa.0 to pa.3) high-speed clock stop v dd = 1.5 v 2.8 3.0 v ddh high-speed clock oscillation (rc oscillation, r crh = 100 k w ) 2.0 v ddl high-speed clock stop 1.0 1.5 2.0 high-speed clock oscillation 2.0 2.7 v sta oscillation start time: within 5 seconds 1.2 v hold 0.9 c g 5.0 25.0 c d 20.0 25.0 30.0 c os 8.0 12.0 16.0 c in 5.0 symbol condition typ. min. max. mea- suring circuit 1 internal low-speed rc oscillator capacitance c xt 10.0 15.0 20.0 v v v v v v pf pf pf pf unit pf (v dd = v ddi = 1.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified)
? semiconductor ML63512A/63514a 15/29 dc characteristics (continued) C0.2 C1.3 C2.5 output current 1 (p0.0 to p0.3) (p1.0 to p1.3) (p6.0 to p6.3) (p9.0 to p9.3) (pa.0 to pa.3) (md) i oh1 v dd = 1.5 v C1.0 C3.5 C6.0 i ol1 1.0 i oh2z output current 2 (p8.0 to p8.3) output current 3 (osc1) 14.0 7.5 3.0 i ol2 20.0 12.0 6.0 v dd = 3.0 v v ddi = 1.5 v v ddi = 3.0 v v oh1 = v dd C 0.5 v v ol1 = 0.5 v v oh2 = v dd v ol2 = 0.5 v i oh3r v dd = v ddh = 3.0 v v oh3r = v ddh C 0.5 v v dd = v ddh = 5.0 v C0.2 C1.5 C2.5 C0.5 C1.8 C3.5 parameter (pin name) symbol condition typ. min. max. mea- suring circuit ma ma m a ma ma ma ma unit 2 (v dd = v ddi = 1.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) C1.5 C5.0 C8.5 v dd = 5.0 v ma 2.5 1.3 0.2 v dd = 1.5 v 6.0 3.0 1.0 v dd = 3.0 v ma ma 8.5 3.7 1.5 v dd = 5.0 v ma 28.0 15.0 8.0 v ddi = 5.0 v ma i ol3r v dd = v ddh = 3.0 v v ol3r = 0.5 v v dd = v ddh = 5.0 v 2.5 1.5 0.2 3.5 1.8 0.5 ma ma i oh3c v dd = v ddh = 3.0 v v oh3c = v ddh C 0.5 v v dd = v ddh = 5.0 v C60 C160 C300 C100 C240 C400 m a m a i ol3c v dd = v ddh = 3.0 v v ol3c = 0.5 v v dd = v ddh = 5.0 v 300 170 60 400 210 100 m a m a output leakage (p0.0 to p0.3) (p1.0 to p1.3) (p6.0 to p6.3) (p8.0 to p8.3) (p9.0 to p9.3) (pa.0 to pa.3) 1.0 i ooh v oh = v dd C1.0 i ool v ol = v ss m a m a
? semiconductor ML63512A/63514a 16/29 dc characteristics (continued) i ih4 v ih4 = v dd v dd = 1.5 v C10.0 C60.0 C120.0 m a C100.0 C350.0 C600.0 i il4 v il4 = v ss (when pulled up) m a parameter (pin name) symbol condition mea- suring circuit unit 1.0 input current 1 (p0.0 to p0.3) (p1.0 to p1.3) (p7.0 to p7.3) (p9.0 to p9.3) (pa.0 to pa.3) i ih1u m a C1.0 C4.0 C8.0 i il1u m a C10.0 C30.0 C60.0 m a 1.0 i ih1z v ih1 = v dd (in a high-impedance state) m a C1.0 i il1z v il1 = v ss (in a high-impedance state) m a C30.0 C170.0 C350.0 i il3 v il3 = v ss (when pulled up) m a 1.0 i ih3r v ih3 = v ddh m a C1.0 i il3r v il3 = v ss m a v dd = 1.5 v v dd = 3.0 v v ih1 = v dd (when pulled up) v il1 = v ss (when pulled up) i ih2 v ih2 = v dd v dd = 1.5 v 1.0 m a C2.0 C20.0 C45.0 m a 3 v dd = v ddh = 3.0 v C70.0 C300.0 C870.0 i il2 v il2 = v ss (when pulled up) m a input current 3 (osc0) input current 2 (resetb) input current 4 (tst1b, tst2b) max. typ. min. v dd = 5.0 v 0.1 m a v dd = 3.0 v (v dd = v ddi = 1.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) C23.0 C90.0 C150.0 m a v dd = 5.0 v C30.0 C120.0 C260.0 m a v dd = 3.0 v C200.0 C450.0 C750.0 m a v dd = v ddh = 5.0 v C220.0 C770.0 C1320.0 m a v dd = 5.0 v
? semiconductor ML63512A/63514a 17/29 dc characteristics (continued) parameter (pin name) symbol condition mea- suring circuit unit max. typ. min. 0.30 0.10 0.05 v t v 1.0 0.5 0.2 v v dd = 3.0 v v dd = 1.5 v hysteresis width (p0.0 to p0.3) (p1.0 to p1.3) (p7.0 to p7.3) (p9.0 to p9.3) (pa.0 to pa.3) (resetb) (tst1b, tst2b) 1.5 1.2 v ih1 v 3.0 2.4 v v dd = 3.0 v v dd = 1.5 v 0.3 0.0 v il1 v 0.6 0.0 v v dd = 3.0 v v dd = 1.5 v input voltage 1 (p0.0 to p0.3) (p1.0 to p1.3) (p7.0 to p7.3) (p9.0 to p9.3) (pa.0 to pa.3) (v dd = v ddi = 1.5 v, v ss = 0 v, ta = C20 to +70c unless otherwise specified) input voltage 2 (osc0) 3.0 2.4 v ih2 v 5.0 4.0 v v dd = v ddh = 5.0 v v dd = v ddh = 3.0 v 0.6 0.0 v 1.0 0.0 v v dd = v ddh = 5.0 v v dd = v ddh = 3.0 v 5.0 4.0 v v dd = 5.0 v 1.0 0.0 v v dd = 5.0 v v il2 0.15 0.00 v il3 v 0.6 0.0 v v dd = 3.0 v v dd = 1.5 v 4 1.50 1.35 v ih3 v 3.0 2.4 v v dd = 3.0 v v dd = 1.5 v input voltage 3 (resetb) (tst1b, tst2b) 5.0 4.0 v v dd = 5.0 v 1.0 0.0 v v dd = 5.0 v 1.50 1.00 0.25 v v dd = 5.0 v
? semiconductor ML63512A/63514a 18/29 hysteresis width input signal v t v dd v ss internal signal v ddl v ss
? semiconductor ML63512A/63514a 19/29 measuring circuit 1 v c l v c h a v ss v dd v ddh v ddl v ddi cb1 cb2 xt0 xt1 q w *1 osc0 e osc1 r c g c b12 , c h c l c o ceramic resonator c l0 c l1 : csa2.00mg (2 mhz) csb1000j (1 mhz) (murata mfg.-make) c b12 c g q w q w r crl *1 crystal oscillator e r r crh rc oscillator *2 rc oscillator c l0 e r ceramic oscillator c l1 : 15 pf : 1 m f : 0.1 m f : 12 pf : 30 pf : 30 pf ceramic resonator *2
? semiconductor ML63512A/63514a 20/29 measuring circuit 2 a *4 v ss v dd v ddh v ddl v ddi *3 v ih v il *3 input logic circuit to determine the specified measuring conditions. *4 measured at the s p ecified out p ut p ins. input output measuring circuit 3 v ss v dd v ddh v ddl v ddi a *5 input output
? semiconductor ML63512A/63514a 21/29 measuring circuit 4 v ss v dd v ddh v ddl v ddi *5 v ih v il *5 measured at the s p ecified in p ut p ins. input output waveform monitoring
? semiconductor ML63512A/63514a 22/29 txd (p3.3) rxd (p3.0) t cyc t ddr t r t f t cwh t cwl t ddr t ds t ds t dh v dd (5.0 v) v ss v dd (5.0 v) v ss v dd (5.0 v) v ss txc (p3.1)/ rxc (p3.2) ac characteristics (serial interface, serial port) (v dd = 0.9 to 5.5 v, v ddh = 1.8 to 5.5 v, v ss = 0 v, v ddi = 0.9 to 5.5 v, ta = C20 to +70 c unless otherwise specified) (1) synchronous communication parameter symbol condition unit txc/rxc input fall time max. typ. min. t f m s 1.0 txc/rxc input rise time t r m s 1.0 0.8 txc/rxc input "l" level pulse width t cwl m s 0.8 txc/rxc input "h" level pulse width t cwh m s 2.0 txc/rxc input cycle time t cyc m s txc/rxc output cycle time t cyc1(o) cpu operating at 32.768 khz m s 30.5 t cyc2(o) cpu operating at 2 mhz v dd = v ddh = 2.7 to 5.5 v m s 0.5 txd output delay time t ddr output load capacitance 10 pf m s 0.4 0.5 rxd input setup time t ds m s 0.8 rxd input hold time t dh m s synchronous communication timing ("h" level = 4.0 v, "l" level = 1.0 v)
? semiconductor ML63512A/63514a 23/29 txd (p3.3) t brt v dd (5.0 v) v ss rxd (p3.0) r brt v dd (5.0 v) v ss (2) uart communication parameter symbol condition unit t brt Ct cr transmit baud rate max. typ. min. t brt t brt = 1/f brt t cr = 1/f osc s t brt t brt +t cr r brt 0.97 receive baud rate r brt s r brt r brt 1.03 r brt = 1/f brt f brt : baud rates (2tbcclk, tbcclk, 1/2tbcclk, timer 0/1 overflow) uart communication timing ("h" level = 4.0 v, "l" level = 1.0 v)
? semiconductor ML63512A/63514a 24/29 ac characteristics parameter symbol condition unit 20 external interrupt enable pulse width (rising edge) max. typ. min. t wh ns (v dd = v ddi = 0.9 to 5.5 v, v ss = 0 v, ta = C20 to + 70c unless otherwise specified) 20 external interrupt enable pulse width (falling edge) t wl ns 13.0 external interrupt disable time t nul interrupt enable, mie = 1 cpu operating under the nop instruction system clock: 32.768 khz m s 65.1 ac characteristics timing t wh t nul t wl t nul p0.0 to p0.3 (interrupt on the rising edge) p0.0 to p0.3 (interrupt on the falling edge) p0.0 to p0.3 (interrupt on both rising and falling edges) t nul
? semiconductor ML63512A/63514a 25/29 comparator electrical characteristics conceptual diagram of comparator supply current the conceptual diagram of the comparator supply current i ddcmp and i dscmp is shown below. parameter symbol condition min. typ. max. unit comparator offset voltage v coff 30 mv comparator conversion time t c system clock: 32.768 khz 183 m s comparator supply current i ddcmp comparator operating 30 90 m a (v dd = 0.9 v, v ss = 0 v, ta = C20 to +70c) comparator input voltage v cin v ss v dd v i dscmp comparator stopped 0.1 m a remarks cmpin cmpref sampling reference voltage comparing reference voltage with input voltage t [ m s] i ddcmp i dscmp i dd (v ss ) [ m a] level detector operating level detector stopped level detector stopped
? semiconductor ML63512A/63514a 26/29 level detector electrical characteristics conceptual diagram of level detector supply current the conceptual diagram of the level detector supply current i ddld and i dsld is shown below. parameter symbol condition min. typ. max. unit level detector input voltage v ld v ss v dd v level dtector supply current t c system clock: 32.768 khz 183 m s i ddld level detector operating 80 130 m a (v dd = 0.9 v, v ss = 0 v, ta = C20 to +70c) level detector conversion time i dsld level detector stopped 0.1 m a remarks ldin0, 1 sampling reference voltage comparing reference voltage with input voltage t [ m s] i ddld i dsld i dd (v ss ) [ m a] level detector operating level detector stopped level detector stopped
? semiconductor ML63512A/63514a 27/29 level detector input levels and output codes (v dd = 0.9 to 1.8 v: when backup is used, v dd = 1.8 to 3.5 v: when backup is not used; v ss = 0 v, ta = C20 to +70 c) input level [v] min. max. 1440/1500 v dd v dd 1306/1500 v dd 1366/1500 v dd 1190/1500 v dd 1250/1500 v dd 1074/1500 v dd 1134/1500 v dd 958/1500 v dd 1018/1500 v dd 842/1500 v dd 902/1500 v dd 726/1500 v dd 786/1500 v dd 610/1500 v dd 670/1500 v dd 494/1500 v dd 554/1500 v dd 378/1500 v dd 438/1500 v dd 262/1500 v dd 322/1500 v dd 146/1500 v dd 206/1500 v dd v ss 88/1500 v dd ldout bit 0 1 1 0 1 0 1 0 1 0 1 0 1 0 bit 1 1 1 1 0 0 1 1 0 0 1 1 0 0 bit 2 1 0 0 0 0 1 1 1 1 0 0 0 0 bit 3 1 1 1 1 1 0 0 0 0 0 0 0 0 level detector operation state off state on state
? semiconductor ML63512A/63514a 28/29 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp48-p-0707-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.13 typ. mirror finish
? semiconductor ML63512A/63514a 29/29 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). tqfp64-p-1010-0.50-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.26 typ. mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-62

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